Collaborative Research: PPoSS: Planning: Efficient Address Translation with Formal Guarantees for Data-Center-Scale Applications

The investigators propose a bottom-up redesign of address translation, a critical bottleneck in the way computers organize where data is stored---whether the computer is a laptop or a massively parallel supercomputer. Address translation gives computer systems flexibility in placing and migrating data between RAM and disk, but it incurs an additional computational cost. The project's novelty is to employ advanced techniques in data structures to accelerate address translation. The project's impact will be to dramatically accelerate a component of all computational tasks, on all computers, from laptops to parallel supercomputers, and for computations ranging from weather simulations to machine learning.

The investigators propose a redesign of TLBs, based on the investigators' recent advances in stable, low-address-complexity hashing. This redesign includes improvements across the hardware/software stack, from the CPU, to hardware accelerators, to RDMA. The goal of this planning project is to establish the viability of the team's approach in preparation for a full proposal to be submitted in the next phase. The investigators are empirically evaluating tacit assumptions behind address-translation design, providing a principled theoretical foundation for end-to-end analysis and design of naming, placement, load balancing, and translation in data-center-scale applications.

This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.