A 10-Bit 100MSPS 0.35 μm Si CMOS pipeline ADC

Qi Yu, Xiang Zhan Wang, Ning Ning, Lin Tang, Hong Bin Li, Mo Hua Yang

Research output: Contribution to conferencePaper

3 Citations (Scopus)

Abstract

Based on the principle of Pipeline ADC, a 4-4-4-bit three-stage 10-bit pipeline analog-to-digital converter (ADC) is presented. Combining with bootstrap circuit and bottom-plate sampling technology, a high linearity on-chip sample-and-hold (S/H) is realized. The preamplifier-latch comparator of the 4-bit flash sub-ADCs is implemented to reduce the comparator latch offset by using zero-crossing technique. In order to reduce common-mode interference, clock feed-through and even order distortion, the full-differential operational trails-conductance amplifiers (OTA) are designed for the residue and S/H circuits. The simulation results show that this ADC achieves over 70dB SFDR with 50MHz Nyquist input frequency at 100MSample/s (MSPS). Fabricated by standard 0.35um 2P3M mixed signal silicon CMOS process, the circuit occupies an area of 12.7mm2.

Original languageEnglish (US)
Pages1523-1525
Number of pages3
StatePublished - Dec 1 2004
Event2004 7th International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT 2004 - Beijing, China
Duration: Oct 18 2004Oct 21 2004

Other

Other2004 7th International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT 2004
CountryChina
CityBeijing
Period10/18/0410/21/04

Fingerprint

Digital to analog conversion
Pipelines
Networks (circuits)
Flip flop circuits
Clocks
Sampling
Silicon

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Yu, Q., Wang, X. Z., Ning, N., Tang, L., Li, H. B., & Yang, M. H. (2004). A 10-Bit 100MSPS 0.35 μm Si CMOS pipeline ADC. 1523-1525. Paper presented at 2004 7th International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT 2004, Beijing, China.
Yu, Qi ; Wang, Xiang Zhan ; Ning, Ning ; Tang, Lin ; Li, Hong Bin ; Yang, Mo Hua. / A 10-Bit 100MSPS 0.35 μm Si CMOS pipeline ADC. Paper presented at 2004 7th International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT 2004, Beijing, China.3 p.
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abstract = "Based on the principle of Pipeline ADC, a 4-4-4-bit three-stage 10-bit pipeline analog-to-digital converter (ADC) is presented. Combining with bootstrap circuit and bottom-plate sampling technology, a high linearity on-chip sample-and-hold (S/H) is realized. The preamplifier-latch comparator of the 4-bit flash sub-ADCs is implemented to reduce the comparator latch offset by using zero-crossing technique. In order to reduce common-mode interference, clock feed-through and even order distortion, the full-differential operational trails-conductance amplifiers (OTA) are designed for the residue and S/H circuits. The simulation results show that this ADC achieves over 70dB SFDR with 50MHz Nyquist input frequency at 100MSample/s (MSPS). Fabricated by standard 0.35um 2P3M mixed signal silicon CMOS process, the circuit occupies an area of 12.7mm2.",
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Yu, Q, Wang, XZ, Ning, N, Tang, L, Li, HB & Yang, MH 2004, 'A 10-Bit 100MSPS 0.35 μm Si CMOS pipeline ADC' Paper presented at 2004 7th International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT 2004, Beijing, China, 10/18/04 - 10/21/04, pp. 1523-1525.

A 10-Bit 100MSPS 0.35 μm Si CMOS pipeline ADC. / Yu, Qi; Wang, Xiang Zhan; Ning, Ning; Tang, Lin; Li, Hong Bin; Yang, Mo Hua.

2004. 1523-1525 Paper presented at 2004 7th International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT 2004, Beijing, China.

Research output: Contribution to conferencePaper

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AU - Yu, Qi

AU - Wang, Xiang Zhan

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AU - Tang, Lin

AU - Li, Hong Bin

AU - Yang, Mo Hua

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N2 - Based on the principle of Pipeline ADC, a 4-4-4-bit three-stage 10-bit pipeline analog-to-digital converter (ADC) is presented. Combining with bootstrap circuit and bottom-plate sampling technology, a high linearity on-chip sample-and-hold (S/H) is realized. The preamplifier-latch comparator of the 4-bit flash sub-ADCs is implemented to reduce the comparator latch offset by using zero-crossing technique. In order to reduce common-mode interference, clock feed-through and even order distortion, the full-differential operational trails-conductance amplifiers (OTA) are designed for the residue and S/H circuits. The simulation results show that this ADC achieves over 70dB SFDR with 50MHz Nyquist input frequency at 100MSample/s (MSPS). Fabricated by standard 0.35um 2P3M mixed signal silicon CMOS process, the circuit occupies an area of 12.7mm2.

AB - Based on the principle of Pipeline ADC, a 4-4-4-bit three-stage 10-bit pipeline analog-to-digital converter (ADC) is presented. Combining with bootstrap circuit and bottom-plate sampling technology, a high linearity on-chip sample-and-hold (S/H) is realized. The preamplifier-latch comparator of the 4-bit flash sub-ADCs is implemented to reduce the comparator latch offset by using zero-crossing technique. In order to reduce common-mode interference, clock feed-through and even order distortion, the full-differential operational trails-conductance amplifiers (OTA) are designed for the residue and S/H circuits. The simulation results show that this ADC achieves over 70dB SFDR with 50MHz Nyquist input frequency at 100MSample/s (MSPS). Fabricated by standard 0.35um 2P3M mixed signal silicon CMOS process, the circuit occupies an area of 12.7mm2.

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Yu Q, Wang XZ, Ning N, Tang L, Li HB, Yang MH. A 10-Bit 100MSPS 0.35 μm Si CMOS pipeline ADC. 2004. Paper presented at 2004 7th International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT 2004, Beijing, China.