Analysis and demonstration of MEM-relay power gating

Hossein Fariborzi, Matthew Spencer, Vaibhav Karkare, Jaeseok Jeon, Rhesa Nathanael, Chengcheng Wang, Fred Chen, Hei Kam, Vincent Pott, Tsu Jae King Liu, Elad Alon, Vladimir Stojanović, Dejan Marković

Research output: Chapter in Book/Report/Conference proceedingConference contribution

23 Scopus citations

Abstract

This paper shows that due to their negligibly low leakage, in certain applications, chips utilizing power gates built even with today's relatively large, high-voltage micro-electro-mechanical (MEM) relays can achieve lower total energy than those built with CMOS transistors. A simple analysis provides design guidelines for off-time and savings estimates as a function of technology parameters, and quantifies the further benefits of scaled relay designs. Finally, we demonstrate a relay chip successfully power-gating a CMOS chip, and show a relay-based timer suitable for self-timed operation.

Original languageEnglish (US)
Title of host publicationIEEE Custom Integrated Circuits Conference 2010, CICC 2010
DOIs
StatePublished - 2010
Externally publishedYes
Event32nd Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2010 - San Jose, CA, United States
Duration: Sep 19 2010Sep 22 2010

Publication series

NameProceedings of the Custom Integrated Circuits Conference

Other

Other32nd Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2010
Country/TerritoryUnited States
CitySan Jose, CA
Period9/19/109/22/10

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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