Behavioral synthesis for hierarchical testability of controller/data path circuits with conditional branches

Sandeep Bhatia, Niraj K. Jha

Research output: Contribution to conferencePaper

17 Scopus citations

Abstract

Most of the existing behavioral synthesis systems put emphasis on optimizing area and performance. Only recently has some research been done to consider testability during behavioral synthesis. In our previous work, we integrated hierarchical testability with behavioral synthesis of simple digital data path circuits to synthesize highly testable circuits. In the current work, we consider the testability of complete controller and data path during behavioral synthesis. The methods presented here can easily handle large and complex behavioral descriptions with loops, conditionals, and allow different scheduling constructs, such as pipelining, multicycling, and chaining. The test set for the combined controller/data path is generated during synthesis in a very short time and near 100% fault coverage is obtained for almost all the synthesized circuits at practically zero overheads.

Original languageEnglish (US)
Pages91-96
Number of pages6
StatePublished - Dec 1 1994
EventProceedings of the IEEE International Conference on Computer Design: VLSI in Computers and Processors - Cambridge, MA, USA
Duration: Oct 10 1994Oct 12 1994

Other

OtherProceedings of the IEEE International Conference on Computer Design: VLSI in Computers and Processors
CityCambridge, MA, USA
Period10/10/9410/12/94

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Hardware and Architecture

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    Bhatia, S., & Jha, N. K. (1994). Behavioral synthesis for hierarchical testability of controller/data path circuits with conditional branches. 91-96. Paper presented at Proceedings of the IEEE International Conference on Computer Design: VLSI in Computers and Processors, Cambridge, MA, USA, .