TY - GEN
T1 - Bridge
T2 - 2nd Workshop on Kernel Isolation, Safety and Verification, KISV 2024
AU - Huang, Gongqi
AU - Schuermann, Leon
AU - Levy, Amit
N1 - Publisher Copyright: © 2024 Copyright held by the owner/author(s).
PY - 2024/11/4
Y1 - 2024/11/4
N2 - Embedded and Internet of Things (IoT) devices are increasingly ubiquitous and process increasingly sensitive data. As a result, such devices must uphold security in addition to functional safety to avoid unintended information leaks. To react this change of environment, developers deploy conventional mechanisms such as memory isolation and priority scheduling to achieve aforementioned goals. While such techniques are resilient against attacks that endanger a device’s functional safety, they are less effective in maintaining security as they ignore information leaks through timing channels, such as through scheduling policy and implicit microarchitectural state. Recent advances in timing-safe systems, in turn, limit themselves to time-shared systems without parallelism. This is problematic in the face of responsiveness and real-time constraints which are often found in embedded devices. This paper explores timing-safety in the space of parallel systems. We introduce Bridge, a new system architecture featuring multiple tasks with different security concerns that can execute in parallel without leaking information due to timing interference.
AB - Embedded and Internet of Things (IoT) devices are increasingly ubiquitous and process increasingly sensitive data. As a result, such devices must uphold security in addition to functional safety to avoid unintended information leaks. To react this change of environment, developers deploy conventional mechanisms such as memory isolation and priority scheduling to achieve aforementioned goals. While such techniques are resilient against attacks that endanger a device’s functional safety, they are less effective in maintaining security as they ignore information leaks through timing channels, such as through scheduling policy and implicit microarchitectural state. Recent advances in timing-safe systems, in turn, limit themselves to time-shared systems without parallelism. This is problematic in the face of responsiveness and real-time constraints which are often found in embedded devices. This paper explores timing-safety in the space of parallel systems. We introduce Bridge, a new system architecture featuring multiple tasks with different security concerns that can execute in parallel without leaking information due to timing interference.
UR - http://www.scopus.com/inward/record.url?scp=85212184688&partnerID=8YFLogxK
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U2 - 10.1145/3698576.3698765
DO - 10.1145/3698576.3698765
M3 - Conference contribution
T3 - KISV 2024 - Proceedings of the 2nd Workshop on Kernel Isolation, Safety and Verification
SP - 16
EP - 22
BT - KISV 2024 - Proceedings of the 2nd Workshop on Kernel Isolation, Safety and Verification
PB - Association for Computing Machinery, Inc
Y2 - 3 November 2024 through 3 November 2024
ER -