Covert and side channels due to processor architecture

Zhenghong Wang; Ruby B. Lee

doi:10.1109/ACSAC.2006.20

Covert and side channels due to processor architecture

Zhenghong Wang, Ruby B. Lee

Princeton University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

170 Scopus citations

Abstract

Information leakage through covert channels and side channels is becoming a serious problem, especially when these are enhanced by modern processor architecture features. We show how processor architecture features such as simultaneous multithreading, control speculation and shared caches can inadvertently accelerate such covert channels or enable new covert channels and side channels. We first illustrate the reality and severity of this problem by describing concrete attacks. We identify two new covert channels. We show orders of magnitude increases in covert channel capacities. We then present two solutions, Selective Partitioning and the novel Random Permutation Cache (RPCache). The RPCache can thwart most cache-based software side channel attacks, with minimal hardware costs and negligible performance impact.

Original language	American English
Title of host publication	Proceedings - Annual Computer Security Applications Conference, ACSAC
Pages	473-482
Number of pages	10
DOIs	https://doi.org/10.1109/ACSAC.2006.20
State	Published - 2006
Event	22nd Annual Computer Security Applications Conference, ACSAC 2006 - Miami Beach, FL, United States Duration: Dec 11 2006 → Dec 15 2006

Publication series

Name	Proceedings - Annual Computer Security Applications Conference, ACSAC

Other

Other	22nd Annual Computer Security Applications Conference, ACSAC 2006
Country/Territory	United States
City	Miami Beach, FL
Period	12/11/06 → 12/15/06

ASJC Scopus subject areas

Software
General Engineering

Access to Document

10.1109/ACSAC.2006.20

Cite this

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title = "Covert and side channels due to processor architecture",

abstract = "Information leakage through covert channels and side channels is becoming a serious problem, especially when these are enhanced by modern processor architecture features. We show how processor architecture features such as simultaneous multithreading, control speculation and shared caches can inadvertently accelerate such covert channels or enable new covert channels and side channels. We first illustrate the reality and severity of this problem by describing concrete attacks. We identify two new covert channels. We show orders of magnitude increases in covert channel capacities. We then present two solutions, Selective Partitioning and the novel Random Permutation Cache (RPCache). The RPCache can thwart most cache-based software side channel attacks, with minimal hardware costs and negligible performance impact.",

author = "Zhenghong Wang and Lee, {Ruby B.}",

year = "2006",

doi = "10.1109/ACSAC.2006.20",

language = "American English",

isbn = "0769527167",

series = "Proceedings - Annual Computer Security Applications Conference, ACSAC",

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note = "22nd Annual Computer Security Applications Conference, ACSAC 2006 ; Conference date: 11-12-2006 Through 15-12-2006",

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Wang, Z & Lee, RB 2006, Covert and side channels due to processor architecture. in Proceedings - Annual Computer Security Applications Conference, ACSAC., 4041191, Proceedings - Annual Computer Security Applications Conference, ACSAC, pp. 473-482, 22nd Annual Computer Security Applications Conference, ACSAC 2006, Miami Beach, FL, United States, 12/11/06. https://doi.org/10.1109/ACSAC.2006.20

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AU - Lee, Ruby B.

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N2 - Information leakage through covert channels and side channels is becoming a serious problem, especially when these are enhanced by modern processor architecture features. We show how processor architecture features such as simultaneous multithreading, control speculation and shared caches can inadvertently accelerate such covert channels or enable new covert channels and side channels. We first illustrate the reality and severity of this problem by describing concrete attacks. We identify two new covert channels. We show orders of magnitude increases in covert channel capacities. We then present two solutions, Selective Partitioning and the novel Random Permutation Cache (RPCache). The RPCache can thwart most cache-based software side channel attacks, with minimal hardware costs and negligible performance impact.

AB - Information leakage through covert channels and side channels is becoming a serious problem, especially when these are enhanced by modern processor architecture features. We show how processor architecture features such as simultaneous multithreading, control speculation and shared caches can inadvertently accelerate such covert channels or enable new covert channels and side channels. We first illustrate the reality and severity of this problem by describing concrete attacks. We identify two new covert channels. We show orders of magnitude increases in covert channel capacities. We then present two solutions, Selective Partitioning and the novel Random Permutation Cache (RPCache). The RPCache can thwart most cache-based software side channel attacks, with minimal hardware costs and negligible performance impact.

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BT - Proceedings - Annual Computer Security Applications Conference, ACSAC

T2 - 22nd Annual Computer Security Applications Conference, ACSAC 2006

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ER -

Covert and side channels due to processor architecture

Abstract

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ASJC Scopus subject areas

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