Design, fabrication and application of 4H-SiC trenched-and-Lmplanted vertical JFETs

TY - GEN

T1 - Design, fabrication and application of 4H-SiC trenched-and-Lmplanted vertical JFETs

AU - Zhao, Jian H.

AU - Alexandrov, Petre

AU - Li, Yuzhu

AU - Li, Larry

AU - Sheng, Kuang

AU - Lebron-Velilla, Ramon

PY - 2006

Y1 - 2006

N2 - This paper reports recent progress in the development of a vertical JFET, the purely vertical JFET based on trenched-and-implanted vertical JFET (TI-VJFET) approach that eliminates the need of epitaxial regrowth at middle of device fabrication and the need of a merged lateral JFET to control the vertical JFET. Different structures have been designed to target breakdown voltages ranging from 600V to 1.2kV. Vertical channel width uniformity has been studied, showing the feasibility of achieving below 0.1 urn variation for reasonably flat wafers of good thickness uniformity. Pitch size of the designs has been reduced compared to early report. Gate trench width has been reduced from 3.8um to 2.3um, aimed at increasing the device current capability. Fabricated device cells have been tested and packaged into multi-cell 30A TI-VJFETs which have been characterized of DC and switching characteristics at room and elevated temperatures. Very fast current rise/fall times of <10ns were observed from RT to 200°C. PSpice model for TI-VJFET has been developed and applied to the performance prediction of 3-phase SiC power inverter, suggesting a high efficiency 97.7% at 200°C junction temperature without using soft-switching scheme. Preliminary experimental demonstration of a PWM-controlled three-phase inverter based on SiC TI-VJFET power board is reported.

AB - This paper reports recent progress in the development of a vertical JFET, the purely vertical JFET based on trenched-and-implanted vertical JFET (TI-VJFET) approach that eliminates the need of epitaxial regrowth at middle of device fabrication and the need of a merged lateral JFET to control the vertical JFET. Different structures have been designed to target breakdown voltages ranging from 600V to 1.2kV. Vertical channel width uniformity has been studied, showing the feasibility of achieving below 0.1 urn variation for reasonably flat wafers of good thickness uniformity. Pitch size of the designs has been reduced compared to early report. Gate trench width has been reduced from 3.8um to 2.3um, aimed at increasing the device current capability. Fabricated device cells have been tested and packaged into multi-cell 30A TI-VJFETs which have been characterized of DC and switching characteristics at room and elevated temperatures. Very fast current rise/fall times of <10ns were observed from RT to 200°C. PSpice model for TI-VJFET has been developed and applied to the performance prediction of 3-phase SiC power inverter, suggesting a high efficiency 97.7% at 200°C junction temperature without using soft-switching scheme. Preliminary experimental demonstration of a PWM-controlled three-phase inverter based on SiC TI-VJFET power board is reported.

KW - High efficiency

KW - High temperature

KW - JFETs

KW - Low resistance

UR - https://www.scopus.com/pages/publications/37849040461

UR - https://www.scopus.com/pages/publications/37849040461#tab=citedBy

U2 - 10.4028/0-87849-425-1.1191

DO - 10.4028/0-87849-425-1.1191

M3 - Conference contribution

SN - 9780878494255

T3 - Materials Science Forum

SP - 1191

EP - 1194

BT - Silicon Carbide and Related Materials - 2005, - Proceedings of the International Conference on Silicon Carbide and Related Materials -2005

PB - Trans Tech Publications Ltd

T2 - International Conference on Silicon Carbide and Related Materials 2005, (ICSCRM 2005)

Y2 - 18 September 2005 through 23 September 2005

ER -