Fast-frequency offset cancellation loop using low-IF receiver and fractional-N PLL

TY - JOUR

T1 - Fast-frequency offset cancellation loop using low-IF receiver and fractional-N PLL

AU - Shin, Sangho

AU - Kim, Kyungmin

AU - Lee, Kwyro

AU - Kang, Sung Mo

N1 - Funding Information: Manuscript received June 9, 2006; revised September 3, 2006. This work was supported in part by the University of California and by the MICROS Research Center. This paper was recommended by Associate Editor S.-I. Liu.

PY - 2007/3/7

Y1 - 2007/3/7

N2 - This brief introduces a simple circuit solution to secure loop stability of an analog-domain fast-frequency offset cancellation loop (OCL). The OCL is composed of a low-IF receiver, phase-domain frequency offset detector (OD), and fractional-N phase-locked loop (PLL). Since the OCL uses a phase-domain OD, a stability concern is essentially needed for its practical use. From the frequency-domain analysis, a PLL bandwidth adaptation by controlling charge-pump currents is proposed to achieve a strong stability with phase-margin of more than 60°. Additionally, a tradeoff between the OCL accuracy and hardware complexity is discussed, and a design example is shown for the 2.4-GHz ZigBee application. With 4-MHz IF, designed for an 0.18-μm CMOS process, our circuit takes 30 μs to reject the frequency offset of +200 kHz within the accuracy of ±5 ppm, with 60-DFFs for a time-to-digital converter.

AB - This brief introduces a simple circuit solution to secure loop stability of an analog-domain fast-frequency offset cancellation loop (OCL). The OCL is composed of a low-IF receiver, phase-domain frequency offset detector (OD), and fractional-N phase-locked loop (PLL). Since the OCL uses a phase-domain OD, a stability concern is essentially needed for its practical use. From the frequency-domain analysis, a PLL bandwidth adaptation by controlling charge-pump currents is proposed to achieve a strong stability with phase-margin of more than 60°. Additionally, a tradeoff between the OCL accuracy and hardware complexity is discussed, and a design example is shown for the 2.4-GHz ZigBee application. With 4-MHz IF, designed for an 0.18-μm CMOS process, our circuit takes 30 μs to reject the frequency offset of +200 kHz within the accuracy of ±5 ppm, with 60-DFFs for a time-to-digital converter.

UR - https://www.scopus.com/pages/publications/34147133411

UR - https://www.scopus.com/pages/publications/34147133411#tab=citedBy

U2 - 10.1109/TCSII.2006.888733

DO - 10.1109/TCSII.2006.888733

M3 - Article

SN - 1549-7747

VL - 54

SP - 272

EP - 276

JO - IEEE Transactions on Circuits and Systems II: Express Briefs

JF - IEEE Transactions on Circuits and Systems II: Express Briefs

IS - 3

ER -