@inproceedings{0444871d3a164f7e99b0b8e518f60fdd,
title = "High-level synthesis of multi-process behavioral descriptions",
abstract = "This paper presents a new high-level synthesis methodology to generate optimized implementations for multi-process behavioral descriptions. The concurrent communicating processes specification paradigm is widely used in digital circuit and system design, and is employed in all popular hardware description languages. It has been shown that inter-process communication and synchronization can result in complex timing inter-dependencies, which significantly affect the performance of a multi-process system. In this paper, we demonstrate that state-of-the-art high-level synthesis tools can generate significantly sub-optimal implementations for behaviors that contain concurrent communicating processes. We present an analysis of how inter-process communication impacts high-level synthesis steps, and describe a new methodology to adapt existing high-level synthesis tools to optimize multi-process descriptions.",
keywords = "Contracts, Digital circuits, Hardware design languages, High level synthesis, National electric code, Optimization methods, Partitioning algorithms, Performance analysis, Resource management, Timing",
author = "Weidong Wang and Anand Raghunathan and Jha, {Niraj K.} and Sujit Dey",
year = "2003",
doi = "https://doi.org/10.1109/ICVD.2003.1183178",
language = "American English",
series = "Proceedings of the IEEE International Conference on VLSI Design",
publisher = "IEEE Computer Society",
pages = "467--473",
booktitle = "Proceedings - 16th International Conference on VLSI Design, VLSI 2003 - concurrently with the 2nd International Conference on Embedded Systems Design",
address = "United States",
note = "16th International Conference on VLSI Design, VLSI 2003 - concurrently with the 2nd International Conference on Embedded Systems Design ; Conference date: 04-01-2003 Through 08-01-2003",
}