Impact of test-structure design and test methods for electromigration testing

Satish Menon, Josef Fazekas, Jochen von Hagen, Linda Head, Colleen H. Ellenwood, Harry A. Schafft

Research output: Contribution to conferencePaperpeer-review

3 Scopus citations

Abstract

The ultimate goal of this work is to develop design guidelines for electromigration test structures and to revise existing standard test methods for fast wafer-level and conventional package-level stress testing. These tests all involve stressing a sample of test structures and measuring their failure times to obtain sample estimates of the median-time-to-failure, t50, and the standard deviation of the loge of the failure times, or sigma (σ). Four test methods (Standard Wafer Level Electromigration Accelerated Test (SWEAT), IsoI-SWEAT, Isothermal, and ASTM) and six test structures (four SWEAT-type and two ASTM-type) were used to stress Al-1% Si metallization (1 μm and 3 μm) lines. It was observed that σ is not affected by test structure design, but is affected by the test method. σ(SWEAT) was the largest and σ(IsoI-SWEAT) was the smallest, quite understandable based on how the stress in the test methods differ. Sigma was also larger for narrower lines. The manner of terminating the test line in the ASTM-type structures did not impact lifetime, except in the narrowest lines, where the lifetime was higher for the structures with split end segments (contrary to expectations). An opening in the passivation over the heat sinks in the SWEAT-type structures did not impact lifetime. A thermal analysis showed that the usual technique of using the fractional change in resistance of the test structure to estimate the joule heating of test lines can lead to underestimates of the stress temperature. The larger the relative resistance of the heat sinks of the test structure, the greater the stress temperature of the test line will be under estimated and the lower the t50 will be. The analysis also helped explain the observed differences in the t50 values for the different test structures.

Original languageEnglish (US)
Pages46-53
Number of pages8
StatePublished - Dec 1 1999
Event1999 IEEE International Integrated Reliability Workshop - Lake Tahoe, CA, USA
Duration: Oct 18 1999Oct 21 1999

Other

Other1999 IEEE International Integrated Reliability Workshop
CityLake Tahoe, CA, USA
Period10/18/9910/21/99

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Industrial and Manufacturing Engineering

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