Leakage power analysis and reduction during behavioral synthesis

Kamal S. Khouri, Niraj Kumar Jha

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Citations (Scopus)

Abstract

This paper presents a high-level leakage power analysis and reduction algorithm. The algorithm uses device level models for leakage to pre-characterize a given register transfer level module library. This is used to estimate the power consumption of a circuit due to leakage. The algorithm can also identify and extract the frequently idle modules in the datapath, which may be targeted for low-leakage optimization. Leakage optimization is based on the use of dual threshold voltage (VT) technology. The algorithm prioritizes modules giving a high-level synthesis (HLS) system an indication of where most gains for leakage reduction may be found. Results show that using a dual-VT library during HLS can reduce leakage power by an average of 59% for the different technology generations. Total power can be reduced by an average of 18.8% to 45.4% for 0.18 μm to 0.07 μm technologies, respectively, compared to register-transfer level (RTL) circuits optimized for switching power only. The contribution of leakage power to overall power consumption of switching power optimized RTL circuits ranges from 23.5% to 54.1%. Our approach reduced these values to 11.4% to 25.9%.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Conference on Computer Design
Subtitle of host publicationVLSI in Computers and Processors
PublisherIEEE
Pages561-564
Number of pages4
StatePublished - Jan 1 2000
Event2000 International Conference on Computer Design - Austin, TX, USA
Duration: Sep 17 2000Sep 20 2000

Other

Other2000 International Conference on Computer Design
CityAustin, TX, USA
Period9/17/009/20/00

Fingerprint

Networks (circuits)
Electric power utilization
Threshold voltage
Electric potential
High level synthesis

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Hardware and Architecture

Cite this

Khouri, K. S., & Jha, N. K. (2000). Leakage power analysis and reduction during behavioral synthesis. In Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors (pp. 561-564). IEEE.
Khouri, Kamal S. ; Jha, Niraj Kumar. / Leakage power analysis and reduction during behavioral synthesis. Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. IEEE, 2000. pp. 561-564
@inproceedings{603a1bbbc9ba46b9a82e5190e6575453,
title = "Leakage power analysis and reduction during behavioral synthesis",
abstract = "This paper presents a high-level leakage power analysis and reduction algorithm. The algorithm uses device level models for leakage to pre-characterize a given register transfer level module library. This is used to estimate the power consumption of a circuit due to leakage. The algorithm can also identify and extract the frequently idle modules in the datapath, which may be targeted for low-leakage optimization. Leakage optimization is based on the use of dual threshold voltage (VT) technology. The algorithm prioritizes modules giving a high-level synthesis (HLS) system an indication of where most gains for leakage reduction may be found. Results show that using a dual-VT library during HLS can reduce leakage power by an average of 59{\%} for the different technology generations. Total power can be reduced by an average of 18.8{\%} to 45.4{\%} for 0.18 μm to 0.07 μm technologies, respectively, compared to register-transfer level (RTL) circuits optimized for switching power only. The contribution of leakage power to overall power consumption of switching power optimized RTL circuits ranges from 23.5{\%} to 54.1{\%}. Our approach reduced these values to 11.4{\%} to 25.9{\%}.",
author = "Khouri, {Kamal S.} and Jha, {Niraj Kumar}",
year = "2000",
month = "1",
day = "1",
language = "English (US)",
pages = "561--564",
booktitle = "Proceedings - IEEE International Conference on Computer Design",
publisher = "IEEE",

}

Khouri, KS & Jha, NK 2000, Leakage power analysis and reduction during behavioral synthesis. in Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. IEEE, pp. 561-564, 2000 International Conference on Computer Design, Austin, TX, USA, 9/17/00.

Leakage power analysis and reduction during behavioral synthesis. / Khouri, Kamal S.; Jha, Niraj Kumar.

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. IEEE, 2000. p. 561-564.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - Leakage power analysis and reduction during behavioral synthesis

AU - Khouri, Kamal S.

AU - Jha, Niraj Kumar

PY - 2000/1/1

Y1 - 2000/1/1

N2 - This paper presents a high-level leakage power analysis and reduction algorithm. The algorithm uses device level models for leakage to pre-characterize a given register transfer level module library. This is used to estimate the power consumption of a circuit due to leakage. The algorithm can also identify and extract the frequently idle modules in the datapath, which may be targeted for low-leakage optimization. Leakage optimization is based on the use of dual threshold voltage (VT) technology. The algorithm prioritizes modules giving a high-level synthesis (HLS) system an indication of where most gains for leakage reduction may be found. Results show that using a dual-VT library during HLS can reduce leakage power by an average of 59% for the different technology generations. Total power can be reduced by an average of 18.8% to 45.4% for 0.18 μm to 0.07 μm technologies, respectively, compared to register-transfer level (RTL) circuits optimized for switching power only. The contribution of leakage power to overall power consumption of switching power optimized RTL circuits ranges from 23.5% to 54.1%. Our approach reduced these values to 11.4% to 25.9%.

AB - This paper presents a high-level leakage power analysis and reduction algorithm. The algorithm uses device level models for leakage to pre-characterize a given register transfer level module library. This is used to estimate the power consumption of a circuit due to leakage. The algorithm can also identify and extract the frequently idle modules in the datapath, which may be targeted for low-leakage optimization. Leakage optimization is based on the use of dual threshold voltage (VT) technology. The algorithm prioritizes modules giving a high-level synthesis (HLS) system an indication of where most gains for leakage reduction may be found. Results show that using a dual-VT library during HLS can reduce leakage power by an average of 59% for the different technology generations. Total power can be reduced by an average of 18.8% to 45.4% for 0.18 μm to 0.07 μm technologies, respectively, compared to register-transfer level (RTL) circuits optimized for switching power only. The contribution of leakage power to overall power consumption of switching power optimized RTL circuits ranges from 23.5% to 54.1%. Our approach reduced these values to 11.4% to 25.9%.

UR - http://www.scopus.com/inward/record.url?scp=0033725173&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0033725173&partnerID=8YFLogxK

M3 - Conference contribution

SP - 561

EP - 564

BT - Proceedings - IEEE International Conference on Computer Design

PB - IEEE

ER -

Khouri KS, Jha NK. Leakage power analysis and reduction during behavioral synthesis. In Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. IEEE. 2000. p. 561-564