TY - JOUR
T1 - MSC-PoL
T2 - Hybrid GaN-Si Multistacked Switched-Capacitor 48-V PwrSiP VRM for Chiplets
AU - Wang, Ping
AU - Chen, Yenan
AU - Szczeszynski, Gregory
AU - Allen, Stephen
AU - Giuliano, David M.
AU - Chen, Minjie
N1 - Publisher Copyright: © 1986-2012 IEEE.
PY - 2023/10/1
Y1 - 2023/10/1
N2 - This article presents a multistack switched-capacitor point-of-load (MSC-PoL) voltage regulation module (VRM) with coupled magnetics for ultrahigh-current chiplet systems. In the MSC-PoL architecture, the stacked switched-capacitor cells split the high input voltage into several intermediate voltage rails, which are loaded with the switched-inductor cells to achieve soft charging and voltage regulation. Automatic capacitor voltage balancing and inductor current sharing are realized during the soft charging process. Many inductors of the switched-inductor cells are coupled into one and operated in interleaving to reduce the inductor current ripple and boost the transient speed. A 48-to-1-V/450-A VRM containing two MSC-PoL modules is built and tested, leveraging high-voltage GaN devices for the front end and high-current silicon devices for the back end. Two ladder-structured coupled inductor designs are developed and compared, one of which installs a leakage magnetic plate to adjust the leakage inductance for lower current ripple. Featuring 3-D stacked packaging, the entire power stage, gate drivers, and bootstrap circuits of one MSC-PoL module are enclosed into a 1 16-brick/0.31-in3/6-mm-thick package. The peak efficiency, the full-load efficiency, and the full-load power density (including both gate loss and size) of the MSC-PoL prototype with and without using the leakage plate are 91.7% and 89.5%, 85.8% and 85.6%, and 621 and 724 W/in3, respectively. The 6-mm-thick MSC-PoL converter can be embedded into the chiplet or CPU socket, enabling power supply in package for extreme efficiency, density, and control bandwidth.
AB - This article presents a multistack switched-capacitor point-of-load (MSC-PoL) voltage regulation module (VRM) with coupled magnetics for ultrahigh-current chiplet systems. In the MSC-PoL architecture, the stacked switched-capacitor cells split the high input voltage into several intermediate voltage rails, which are loaded with the switched-inductor cells to achieve soft charging and voltage regulation. Automatic capacitor voltage balancing and inductor current sharing are realized during the soft charging process. Many inductors of the switched-inductor cells are coupled into one and operated in interleaving to reduce the inductor current ripple and boost the transient speed. A 48-to-1-V/450-A VRM containing two MSC-PoL modules is built and tested, leveraging high-voltage GaN devices for the front end and high-current silicon devices for the back end. Two ladder-structured coupled inductor designs are developed and compared, one of which installs a leakage magnetic plate to adjust the leakage inductance for lower current ripple. Featuring 3-D stacked packaging, the entire power stage, gate drivers, and bootstrap circuits of one MSC-PoL module are enclosed into a 1 16-brick/0.31-in3/6-mm-thick package. The peak efficiency, the full-load efficiency, and the full-load power density (including both gate loss and size) of the MSC-PoL prototype with and without using the leakage plate are 91.7% and 89.5%, 85.8% and 85.6%, and 621 and 724 W/in3, respectively. The 6-mm-thick MSC-PoL converter can be embedded into the chiplet or CPU socket, enabling power supply in package for extreme efficiency, density, and control bandwidth.
KW - CPU voltage regulation module (VRM)
KW - Chiplet
KW - coupled inductor
KW - point of load (PoL)
KW - power supply in package (PwrSiP)
KW - switched capacitor (SC)
UR - http://www.scopus.com/inward/record.url?scp=85164442269&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85164442269&partnerID=8YFLogxK
U2 - 10.1109/TPEL.2023.3293022
DO - 10.1109/TPEL.2023.3293022
M3 - Article
SN - 0885-8993
VL - 38
SP - 12815
EP - 12833
JO - IEEE Transactions on Power Electronics
JF - IEEE Transactions on Power Electronics
IS - 10
ER -