TY - GEN
T1 - Solution-based fabrication of P-channel and N-channel thin-film transistors using random and aligned carbon nanotube networks
AU - Duan, Yan
AU - Juhala, Jason L.
AU - Griffith, Benjamin W.
AU - Uwizeye, Vianney J.
AU - Xue, Wei
PY - 2012/12/1
Y1 - 2012/12/1
N2 - Since discovered in the early 1990s, single-walled carbon nanotubes (SWNTs) have attracted significant attention for many research fields. In the long term, micro-and nanoelectronics are considered to be one of the most valuable applications of SWNTs. The development of the next generation devices involves the mass fabrication and integration of SWNT field-effect transistors (FETs) to form logic gates, which are the basic units of integrated circuits (ICs). To create logic gates, both p- and n-type SWNT FETs are needed. However, the SWNT FETs are typically p-type in air without special treatment, with holes as the majority charge carriers in SWNTs. Here in this paper, we investigate the pchannel and n-channel SWNT FETs using two solution-based fabrication processes. One method is to use layer-by-layer selfassembly to create SWNT random networks and the other is based on dielectrophoresis-aligned SWNTs. A low-cost, easyto- control method is introduced to convert p-type FETs to ntype. By coating a polyethylenimine (PEI) layer on the surface, the transistor demonstrates the typical n-channel characteristics. The resulting devices are air-stable outside a vacuum or an inert environment. The combination of the simple fabrication methods, easy conversion of the devices, and satisfactory device performance can promote further development of nanotube-based electronics.
AB - Since discovered in the early 1990s, single-walled carbon nanotubes (SWNTs) have attracted significant attention for many research fields. In the long term, micro-and nanoelectronics are considered to be one of the most valuable applications of SWNTs. The development of the next generation devices involves the mass fabrication and integration of SWNT field-effect transistors (FETs) to form logic gates, which are the basic units of integrated circuits (ICs). To create logic gates, both p- and n-type SWNT FETs are needed. However, the SWNT FETs are typically p-type in air without special treatment, with holes as the majority charge carriers in SWNTs. Here in this paper, we investigate the pchannel and n-channel SWNT FETs using two solution-based fabrication processes. One method is to use layer-by-layer selfassembly to create SWNT random networks and the other is based on dielectrophoresis-aligned SWNTs. A low-cost, easyto- control method is introduced to convert p-type FETs to ntype. By coating a polyethylenimine (PEI) layer on the surface, the transistor demonstrates the typical n-channel characteristics. The resulting devices are air-stable outside a vacuum or an inert environment. The combination of the simple fabrication methods, easy conversion of the devices, and satisfactory device performance can promote further development of nanotube-based electronics.
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U2 - https://doi.org/10.1115/IMECE2012-86353
DO - https://doi.org/10.1115/IMECE2012-86353
M3 - Conference contribution
SN - 9780791845257
T3 - ASME International Mechanical Engineering Congress and Exposition, Proceedings (IMECE)
SP - 97
EP - 102
BT - ASME 2012 International Mechanical Engineering Congress and Exposition, IMECE 2012
T2 - ASME 2012 International Mechanical Engineering Congress and Exposition, IMECE 2012
Y2 - 9 November 2012 through 15 November 2012
ER -