Statistical optimization of FinFET processor architectures under PVT variations using dual device-Type assignment

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2 Citations (Scopus)

Abstract

With semiconductor technology scaling to the 22nm node and beyond, fin field-effect transistor (FinFET) has started replacing complementary metal-oxide semiconductor (CMOS), thanks to its superior control of short-channel effects and much lower leakage current. However, process, supply voltage, and temperature (PVT) variations across the integrated circuit (IC) become worse with technology scaling. Thus, to analyze timing, leakage power, and dynamic power under PVT variations, statistical analysis/optimization techniques are more suitable than traditional static timing/power analysis and optimization counterparts. In this article, we propose a statistical optimization framework using dual device-Type assignment at the architecture level under PVT variations that takes spatial correlations into account and leverages circuit-level statistical analysis techniques. To the best of our knowledge, this is the first work to study statistical optimization at the system level under PVT variations. Simulation results show that leakage power yield and dynamic power yield at the mean value of the baseline can be improved by up to 44.2% and 21.2%, respectively, with no loss in timing yield for a single-core processor and up to 43.0% and 50.0%, respectively, without any loss in timing yield for an 8-core chip multiprocessor (CMP), at little area overhead. Under the same (99.0%) power yield constraints, leakage power and dynamic power are reduced by up to 91.2% and 4.3%, respectively, for a singlecore processor, and up to 44.6% and 12.5%, respectively, for an 8-core CMP,with no loss in timing yield.We also show that optimizations performed without taking module-To-module and core-To-core spatial correlations into account overestimate yield, establishing the importance of taking such correlations into account.

Original languageEnglish (US)
Article number3
JournalACM Journal on Emerging Technologies in Computing Systems
Volume14
Issue number1
DOIs
StatePublished - Sep 1 2017

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Field effect transistors
Electric potential
Statistical methods
Temperature
Leakage currents
Integrated circuits
Semiconductor materials
Networks (circuits)
Metals

All Science Journal Classification (ASJC) codes

  • Software
  • Electrical and Electronic Engineering
  • Hardware and Architecture

Cite this

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title = "Statistical optimization of FinFET processor architectures under PVT variations using dual device-Type assignment",
abstract = "With semiconductor technology scaling to the 22nm node and beyond, fin field-effect transistor (FinFET) has started replacing complementary metal-oxide semiconductor (CMOS), thanks to its superior control of short-channel effects and much lower leakage current. However, process, supply voltage, and temperature (PVT) variations across the integrated circuit (IC) become worse with technology scaling. Thus, to analyze timing, leakage power, and dynamic power under PVT variations, statistical analysis/optimization techniques are more suitable than traditional static timing/power analysis and optimization counterparts. In this article, we propose a statistical optimization framework using dual device-Type assignment at the architecture level under PVT variations that takes spatial correlations into account and leverages circuit-level statistical analysis techniques. To the best of our knowledge, this is the first work to study statistical optimization at the system level under PVT variations. Simulation results show that leakage power yield and dynamic power yield at the mean value of the baseline can be improved by up to 44.2{\%} and 21.2{\%}, respectively, with no loss in timing yield for a single-core processor and up to 43.0{\%} and 50.0{\%}, respectively, without any loss in timing yield for an 8-core chip multiprocessor (CMP), at little area overhead. Under the same (99.0{\%}) power yield constraints, leakage power and dynamic power are reduced by up to 91.2{\%} and 4.3{\%}, respectively, for a singlecore processor, and up to 44.6{\%} and 12.5{\%}, respectively, for an 8-core CMP,with no loss in timing yield.We also show that optimizations performed without taking module-To-module and core-To-core spatial correlations into account overestimate yield, establishing the importance of taking such correlations into account.",
author = "Ye Yu and Jha, {Niraj Kumar}",
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N2 - With semiconductor technology scaling to the 22nm node and beyond, fin field-effect transistor (FinFET) has started replacing complementary metal-oxide semiconductor (CMOS), thanks to its superior control of short-channel effects and much lower leakage current. However, process, supply voltage, and temperature (PVT) variations across the integrated circuit (IC) become worse with technology scaling. Thus, to analyze timing, leakage power, and dynamic power under PVT variations, statistical analysis/optimization techniques are more suitable than traditional static timing/power analysis and optimization counterparts. In this article, we propose a statistical optimization framework using dual device-Type assignment at the architecture level under PVT variations that takes spatial correlations into account and leverages circuit-level statistical analysis techniques. To the best of our knowledge, this is the first work to study statistical optimization at the system level under PVT variations. Simulation results show that leakage power yield and dynamic power yield at the mean value of the baseline can be improved by up to 44.2% and 21.2%, respectively, with no loss in timing yield for a single-core processor and up to 43.0% and 50.0%, respectively, without any loss in timing yield for an 8-core chip multiprocessor (CMP), at little area overhead. Under the same (99.0%) power yield constraints, leakage power and dynamic power are reduced by up to 91.2% and 4.3%, respectively, for a singlecore processor, and up to 44.6% and 12.5%, respectively, for an 8-core CMP,with no loss in timing yield.We also show that optimizations performed without taking module-To-module and core-To-core spatial correlations into account overestimate yield, establishing the importance of taking such correlations into account.

AB - With semiconductor technology scaling to the 22nm node and beyond, fin field-effect transistor (FinFET) has started replacing complementary metal-oxide semiconductor (CMOS), thanks to its superior control of short-channel effects and much lower leakage current. However, process, supply voltage, and temperature (PVT) variations across the integrated circuit (IC) become worse with technology scaling. Thus, to analyze timing, leakage power, and dynamic power under PVT variations, statistical analysis/optimization techniques are more suitable than traditional static timing/power analysis and optimization counterparts. In this article, we propose a statistical optimization framework using dual device-Type assignment at the architecture level under PVT variations that takes spatial correlations into account and leverages circuit-level statistical analysis techniques. To the best of our knowledge, this is the first work to study statistical optimization at the system level under PVT variations. Simulation results show that leakage power yield and dynamic power yield at the mean value of the baseline can be improved by up to 44.2% and 21.2%, respectively, with no loss in timing yield for a single-core processor and up to 43.0% and 50.0%, respectively, without any loss in timing yield for an 8-core chip multiprocessor (CMP), at little area overhead. Under the same (99.0%) power yield constraints, leakage power and dynamic power are reduced by up to 91.2% and 4.3%, respectively, for a singlecore processor, and up to 44.6% and 12.5%, respectively, for an 8-core CMP,with no loss in timing yield.We also show that optimizations performed without taking module-To-module and core-To-core spatial correlations into account overestimate yield, establishing the importance of taking such correlations into account.

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