Abstract
With semiconductor technology scaling to the 22nm node and beyond, fin field-effect transistor (FinFET) has started replacing complementary metal-oxide semiconductor (CMOS), thanks to its superior control of short-channel effects and much lower leakage current. However, process, supply voltage, and temperature (PVT) variations across the integrated circuit (IC) become worse with technology scaling. Thus, to analyze timing, leakage power, and dynamic power under PVT variations, statistical analysis/optimization techniques are more suitable than traditional static timing/power analysis and optimization counterparts. In this article, we propose a statistical optimization framework using dual device-Type assignment at the architecture level under PVT variations that takes spatial correlations into account and leverages circuit-level statistical analysis techniques. To the best of our knowledge, this is the first work to study statistical optimization at the system level under PVT variations. Simulation results show that leakage power yield and dynamic power yield at the mean value of the baseline can be improved by up to 44.2% and 21.2%, respectively, with no loss in timing yield for a single-core processor and up to 43.0% and 50.0%, respectively, without any loss in timing yield for an 8-core chip multiprocessor (CMP), at little area overhead. Under the same (99.0%) power yield constraints, leakage power and dynamic power are reduced by up to 91.2% and 4.3%, respectively, for a singlecore processor, and up to 44.6% and 12.5%, respectively, for an 8-core CMP,with no loss in timing yield.We also show that optimizations performed without taking module-To-module and core-To-core spatial correlations into account overestimate yield, establishing the importance of taking such correlations into account.
| Original language | English (US) |
|---|---|
| Article number | 3 |
| Journal | ACM Journal on Emerging Technologies in Computing Systems |
| Volume | 14 |
| Issue number | 1 |
| DOIs | |
| State | Published - Sep 2017 |
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All Science Journal Classification (ASJC) codes
- Software
- Electrical and Electronic Engineering
- Hardware and Architecture
Keywords
- Chip multiprocessor
- FinFET
- PVT variations
- Statistical analysis
- Statistical optimization
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Statistical optimization of FinFET processor architectures under PVT variations using dual device-Type assignment. / Yu, Ye; Jha, Niraj K.
In: ACM Journal on Emerging Technologies in Computing Systems, Vol. 14, No. 1, 3, 09.2017.Research output: Contribution to journal › Article
TY - JOUR
T1 - Statistical optimization of FinFET processor architectures under PVT variations using dual device-Type assignment
AU - Yu, Ye
AU - Jha, Niraj K.
PY - 2017/9
Y1 - 2017/9
N2 - With semiconductor technology scaling to the 22nm node and beyond, fin field-effect transistor (FinFET) has started replacing complementary metal-oxide semiconductor (CMOS), thanks to its superior control of short-channel effects and much lower leakage current. However, process, supply voltage, and temperature (PVT) variations across the integrated circuit (IC) become worse with technology scaling. Thus, to analyze timing, leakage power, and dynamic power under PVT variations, statistical analysis/optimization techniques are more suitable than traditional static timing/power analysis and optimization counterparts. In this article, we propose a statistical optimization framework using dual device-Type assignment at the architecture level under PVT variations that takes spatial correlations into account and leverages circuit-level statistical analysis techniques. To the best of our knowledge, this is the first work to study statistical optimization at the system level under PVT variations. Simulation results show that leakage power yield and dynamic power yield at the mean value of the baseline can be improved by up to 44.2% and 21.2%, respectively, with no loss in timing yield for a single-core processor and up to 43.0% and 50.0%, respectively, without any loss in timing yield for an 8-core chip multiprocessor (CMP), at little area overhead. Under the same (99.0%) power yield constraints, leakage power and dynamic power are reduced by up to 91.2% and 4.3%, respectively, for a singlecore processor, and up to 44.6% and 12.5%, respectively, for an 8-core CMP,with no loss in timing yield.We also show that optimizations performed without taking module-To-module and core-To-core spatial correlations into account overestimate yield, establishing the importance of taking such correlations into account.
AB - With semiconductor technology scaling to the 22nm node and beyond, fin field-effect transistor (FinFET) has started replacing complementary metal-oxide semiconductor (CMOS), thanks to its superior control of short-channel effects and much lower leakage current. However, process, supply voltage, and temperature (PVT) variations across the integrated circuit (IC) become worse with technology scaling. Thus, to analyze timing, leakage power, and dynamic power under PVT variations, statistical analysis/optimization techniques are more suitable than traditional static timing/power analysis and optimization counterparts. In this article, we propose a statistical optimization framework using dual device-Type assignment at the architecture level under PVT variations that takes spatial correlations into account and leverages circuit-level statistical analysis techniques. To the best of our knowledge, this is the first work to study statistical optimization at the system level under PVT variations. Simulation results show that leakage power yield and dynamic power yield at the mean value of the baseline can be improved by up to 44.2% and 21.2%, respectively, with no loss in timing yield for a single-core processor and up to 43.0% and 50.0%, respectively, without any loss in timing yield for an 8-core chip multiprocessor (CMP), at little area overhead. Under the same (99.0%) power yield constraints, leakage power and dynamic power are reduced by up to 91.2% and 4.3%, respectively, for a singlecore processor, and up to 44.6% and 12.5%, respectively, for an 8-core CMP,with no loss in timing yield.We also show that optimizations performed without taking module-To-module and core-To-core spatial correlations into account overestimate yield, establishing the importance of taking such correlations into account.
KW - Chip multiprocessor
KW - FinFET
KW - PVT variations
KW - Statistical analysis
KW - Statistical optimization
UR - http://www.scopus.com/inward/record.url?scp=85030214301&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85030214301&partnerID=8YFLogxK
U2 - https://doi.org/10.1145/3110714
DO - https://doi.org/10.1145/3110714
M3 - Article
VL - 14
JO - ACM Journal on Emerging Technologies in Computing Systems
JF - ACM Journal on Emerging Technologies in Computing Systems
SN - 1550-4832
IS - 1
M1 - 3
ER -