Synthesis of Heterogeneous Distributed Architectures for Memory-intensive Applications

Keyphrases

• Array Data 100%
• Distributed Architecture 100%
• Memory-intensive Applications 100%
• High-level Synthesis 50%
• Performance Speedup 50%
• Data Access 25%
• Synthesis Methods 25%
• Partitioning Method 25%
• Affine 25%
• Improvement Strategies 25%
• Iterative Improvement 25%
• Benchmark Applications 25%
• Access Pattern 25%
• Index Function 25%
• General Techniques 25%
• Memory Architecture 25%
• Memory Organization 25%
• Single chip 25%
• General-purpose Computing 25%
• Performance Speed 25%
• Array Indexing 25%
• Physical Memory 25%
• Data Access Pattern 25%
• ASIC Design 25%
• Min-cut 25%
• Data References 25%
• Memory Size 25%
• Distributed Logic 25%
• Access Latency 25%
• Access Locality 25%
• Loop Nest 25%
• Irregular Array 25%
• Balanced Workload 25%
• Sub-behaviour 25%
• Inter-partition Communication 25%

Computer Science

• Application Specific Integrated Circuit 100%
• Intensive Application 100%
• Distributed Architecture 100%
• Data Array 100%
• High Level Synthesis 66%
• Bandwidth Requirement 33%
• Partitioning Technique 33%
• Data Access 33%
• Speed-up 33%
• Application Benchmark 33%
• Feasible Solution 33%
• Access Pattern 33%
• Memory Architecture 33%
• single-chip 33%
• Reference Data 33%
• Physical Memory 33%
• Data Access Pattern 33%
• Affine Function 33%
• Access Requirement 33%