The XTREM Power and Performance Simulator for the Intel XScale Core: Design and Experiences

Gilberto Contreras, Margaret Rose Martonosi, Jinzhang Peng, Guei Yuan Lueh, Roy Ju

Research output: Contribution to journalArticle

25 Citations (Scopus)

Abstract

Managing power concerns in microprocessors has become a pressing research problem across the domains of computer architecture, CAD, and compilers. As a result, several parameterized cycle-level power simulators have been introduced. While these simulators can be quite useful for microarchitectural studies, their generality limits how accurate they can be for any one chip family. Furthermore, their hardware focus means that they do not explicitly enable studying the interaction of different software layers, such as Java applications and their underlying runtime system software. This paper describes and evaluates XTREM, a power-simulation tool tailored for the Intel XScale microarchitecture. In building XTREM, our goals were to develop a microarchitecture simulator that, while still offering size parameterizations for cache and other structures, more accurately reflected a realistic processor pipeline. We present a detailed set of validations based on multimeter power measurements and hardware performance counter sampling. XTREM exhibits an average performance error of only 6.5% and an even smaller average power error: 4%. The paper goes on to present an application study enabled by the simulator. Namely, we use XTREM to produce an energy consumption breakdown for Java CDC and CLDC applications. Our simulator measurements indicate that a large percentage of the total energy consumption (up to 35%) is devoted to the virtual machine's support functions.

Original languageEnglish (US)
Number of pages1
JournalACM Transactions on Embedded Computing Systems
Volume6
Issue number1
DOIs
StatePublished - Jan 1 2007

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Simulators
Energy utilization
Hardware
Computer architecture
Parameterization
Microprocessor chips
Computer aided design
Pipelines
Sampling

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture

Cite this

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abstract = "Managing power concerns in microprocessors has become a pressing research problem across the domains of computer architecture, CAD, and compilers. As a result, several parameterized cycle-level power simulators have been introduced. While these simulators can be quite useful for microarchitectural studies, their generality limits how accurate they can be for any one chip family. Furthermore, their hardware focus means that they do not explicitly enable studying the interaction of different software layers, such as Java applications and their underlying runtime system software. This paper describes and evaluates XTREM, a power-simulation tool tailored for the Intel XScale microarchitecture. In building XTREM, our goals were to develop a microarchitecture simulator that, while still offering size parameterizations for cache and other structures, more accurately reflected a realistic processor pipeline. We present a detailed set of validations based on multimeter power measurements and hardware performance counter sampling. XTREM exhibits an average performance error of only 6.5{\%} and an even smaller average power error: 4{\%}. The paper goes on to present an application study enabled by the simulator. Namely, we use XTREM to produce an energy consumption breakdown for Java CDC and CLDC applications. Our simulator measurements indicate that a large percentage of the total energy consumption (up to 35{\%}) is devoted to the virtual machine's support functions.",
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The XTREM Power and Performance Simulator for the Intel XScale Core : Design and Experiences. / Contreras, Gilberto; Martonosi, Margaret Rose; Peng, Jinzhang; Lueh, Guei Yuan; Ju, Roy.

In: ACM Transactions on Embedded Computing Systems, Vol. 6, No. 1, 01.01.2007.

Research output: Contribution to journalArticle

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